1. Field of the Invention
The present invention relates to a thin film transistor array panel, in particular to a visual inspection means and a method of performing visual inspection in a thin film transistor array panel having a gate driving circuit integrated therein.
2. Description of the Related Art
A thin film transistor array panel is used as a circuit panel for driving each of pixels independently in a liquid crystal display (LCD) or an organic electroluminescence (EL) display, etc. In the thin film transistor panel, a scan signal wire or a gate wire for transferring a scan signal and an image signal wire or a data wire for transferring an image signal are formed. Also, a thin film transistor connected to the gate wire and the data wire, a pixel electrode connected to the thin film transistor, a gate insulating layer for covering and insulating the gate wire and a passivation layer for covering and for insulating the thin film transistor and the data wire are formed therein. The thin film transistor comprises a semiconductor layer forming a channel together with a gate electrode that is a part of the gate wire, a source electrode and a drain electrode that is a part of the data wire, the gate insulating layer and the passivation layer. The thin film transistor is a switching element that transmits the image signal transmitted through the data wire to the pixel electrode depending on the scan signal transmitted through the gate wire.
An LCD is a representative of display devices using such a thin film transistor panel, and especially a middle-small type LCD, such as a reflection type or semi-transmittance type mostly, employs a COG (chip on glass) type. In this case, visual inspection (VI) or gross test (GT) is done before a COG IC mounting process so as to save expensive COG ICs, polarizers and a compensating film and to increase the yield. It is difficult to apply GT to a practical process since the test requires an expensive equipment and furthermore a long processing time. In addition, a currently available VI is performed after forming a wire for inspection to connect gate lines and data lines between the COG terminals or to its opposite side to perform the VI, then a diamond-cutting is done together with a panel or a laser-cutting is done to divide the wire for inspection. In this case, in such a cutting process, pollutant particles are generated or the wire is corroded through a cut side thereof, and thereby degrading the reliability.
In the meanwhile, TFT panels can be manufactured by a method in which a driving integrated circuit is directly formed on the thin film transistor, either partially or as a whole. As such example, there are a poly silicon thin film transistor panel (Poly TFT Panel) and an amorphous driving integrated circuit panel (a-si IC Panel). In the method of directly forming the driving IC on the TFT panel as a whole, GT can be performed by the TFT itself. However, the method of directly forming only a portion of the driving IC on the TFT panel needs an expensive equipment to perform GT.
Furthermore, it is hard to employ a laser-cutting after inspection since the driving IC formed on the TFT works as impediments on laser-cutting and, due to forming the TFT panel and a color filter panel in a same size, a space for laser-cutting is not easy to obtain.
The present invention increases the reliability of a liquid crystal display by solving the problems.
The present invention provides a means for performing a visual inspection in a thin film transistor having a driving integrated circuit.
The present invention also provides methods for performing visual inspection in a thin film transistor having a driving integrated circuit.
In one aspect, the present invention provides a thin film transistor panel comprising a logic circuit for VI connected between a gate driving circuit and a gate line to apply a gate inspection signal.
In detail, a thin film transistor panel includes an insulating substrate having a display area and a surrounding area, a first signal line formed on the insulating substrate, a second signal line formed on the insulating substrate and insulated with and intersecting the first signal line to define the display area, a plurality of driving signal lines formed on the surrounding area of the insulating substrate and connected to a Voff voltage applying terminal, a plurality of inspection signal lines formed on the surrounding area of the insulating substrate, a first thin film transistor for inspection having a drain electrode coupled to the first signal line, a source electrode coupled to any one of the inspection signal lines and a gate electrode coupled to any one of the driving signal lines, and a second thin film transistor for inspection having a drain electrode coupled to the second signal line, a source electrode coupled to any one of the inspection signal lines and a gate electrode coupled to any one of the driving signal lines.
The inspection signal line connected to the second thin film transistor for inspection comprises a first inspection signal line and a second inspection signal line. The second thin film transistor for inspection may be alternatingly connected to the first inspection signal line and the second inspection signal line. The first inspection signal line connected to the first thin film transistor for inspection comprise third and fourth inspection signal lines. The first thin film transistor for inspection may be alternatingly connected to the third inspection signal line and the fourth inspection signal line.
In addition, the inspection signal line connected to the second thin film transistor for inspection comprises first, second and third inspection signal lines. The second thin film transistor for inspection may be connected to the first, second and third inspection signal lines in turn. The inspection signal line connected to the first thin film transistor for inspection comprises fourth and fifth inspection signal lines. The first thin film transistor for inspection is alternatingly connected to the fourth and fifth inspection signal lines.
The driving signal line connected to the second thin film transistor for inspection comprises first, second and third driving signal lines. The second thin film transistor for inspection may be connected to the first, second and third driving signal lines in turn.
A detailed structure of a thin film transistor panel having a thin film transistor for inspection is as below.
The thin film transistor panel includes an insulating substrate having a display area and a surrounding area, a gate line formed on the insulating substrate, a data driving signal line formed on the surrounding area of the insulating substrate, a data inspection signal line formed on the surrounding area of the insulating area, a gate insulating layer formed on the gate lines, the data driving signal lines and the data inspection signal lines, a semiconductor pattern formed on the gate insulating layer, at least a portion thereof overlapping the data driving signal lines, first and second ohmic contact layers formed on the first semiconductor pattern and exposing therebetween a portion of the first semiconductor pattern corresponding to the data driving signal lines, a data line formed on the gate insulating layer and intersecting the gate lines to define the display area, at least a portion thereof being formed on the second ohmic contact layer, a first electrode for inspection formed on the gate insulating layer, at least a portion thereof being formed on the first ohmic contact layer, a passivation layer formed on the data lines and the first electrode for inspection, and a first connection portion formed on the passivation layer and connecting the data inspection signal lines and the first electrode for inspection.
The thin film transistor panel may further include a gate driving signal line formed on the surrounding area of the insulating substrate, a gate inspection signal line formed on the surrounding area of the insulating substrate, a second semiconductor pattern formed on the gate insulating layer, at least a portion thereof overlapping the gate driving signal line, third and fourth ohmic contact layers formed on the second semiconductor pattern and exposing therebetween a portion of the second semiconductor pattern corresponding to the gate driving signal line, a second electrode for inspection formed on the gate insulating layer, at least a portion thereof being formed on the third ohmic contact layer, a third electrode for inspection formed on the gate insulating layer, at least a portion thereof being formed on the fourth ohmic contact layer, a second connection portion formed on the passivation layer and connecting the gate line and the third electrode for inspection, and a third connection portion formed on the passivation layer and connecting the gate inspection signal line and the second electrode for inspection. The first to fourth ohmic contact layers are formed on an entire surface of the data line and the first to the third electrodes for inspection, respectively.
The thin film transistor panel may further include a transmission gate circuit formed on the surrounding area, an output terminal thereof being connected to the data lines, and a short strip connected to an input terminal of the transmission gate circuit, or further include a transmission gate circuit formed on the surrounding area of the insulating substrate and having an output connected to the data lines, a driving signal line formed on the surrounding area of the insulating substrate and connected to Voff voltage applying terminal, an inspection signal line formed on the surrounding area of the insulating substrate, and a thin film transistor for inspection having a drain electrode coupled to the data lines, a source electrode coupled to the inspection signal line and a gate electrode coupled to the driving signal line. In addition, the inspection signal line connected to the thin film transistor for inspection comprises first and second inspection signal lines, and it is preferable that the thin film transistor for inspection is connected to the first inspection signal and the second inspection signal in turn.
In the meantime, the thin film transistor panel further includes a first short strip connected to the data lines in odd number and a second short strip connected the data lines in even number.
Even though not forming such a logic circuit, in a liquid crystal display including a first insulating substrate having a display area and a surrounding area, a plurality of gate lines formed on the first insulating substrate, a plurality of data lines formed on the first insulating substrate and intersecting the gate lines to define the display area, a pixel thin film transistor formed on the first insulating substrate and connected to the gate lines and the data lines, a pixel electrode formed on the display area and connected to the pixel thin film transistor, a gate driving circuit formed on the surrounding area of the thin film transistor and connected to the gate lines and having first and second clock signal terminals, an on and off power terminal and a scan start terminal, a driving signal line formed on the surrounding area of the first insulating substrate and a driving signal terminal, an inspection signal line on the surrounding area of the first insulating substrate and an inspection signal terminal, a thin film transistor for inspection having a drain electrode coupled to the data lines, a source electrode coupled to the inspection signal line and a gate electrode coupled to the driving signal line, a common voltage terminal formed on the surrounding area of the first insulating area, a second insulating substrate disposed opposite the first insulating substrate, a common electrode formed on the second insulating substrate and connected to the common voltage terminal, and a liquid crystal material injected between the first and the second insulating substrates, visual inspection is performed by applying Von voltages to the first and second clock signal terminals of the gate driving circuit, the on and off power terminal, the scan start terminal and the driving signal terminal, and by applying a common voltage to the common voltage terminal.
Alternatively, in a liquid crystal display including a first insulating substrate consisting of a display area and a surrounding area, a plurality of gate lines formed on the first insulating substrate, a plurality of data lines formed on the first insulating substrate and intersecting the gate lines to define the display area, a pixel thin film transistor formed on the first insulating substrate and connected to the gate lines and the data lines, a pixel electrode formed on the display area and connected to the pixel thin film transistor, a gate driving circuit formed on the surrounding area of the thin film transistor and connected to the gate lines and having first and second clock signal terminals, an on and off power terminal and a scan start terminal, a short strip formed on the surrounding area of the first insulating area and connected to the data lines, a common voltage terminal formed on the surrounding area of the first insulating area, a second insulating substrate disposed opposite the first insulating substrate, a common electrode formed on the second insulating substrate and connected to the common voltage terminal, and a liquid crystal material injected between the first and second insulating substrates, it is possible to perform visual inspection by applying Von voltages to the first and second clock signal terminals of the gate driving circuit, the on and off power terminal, the scan start terminal and the driving signal terminal, and applying an inspection signal to the short strip and applying a common voltage to the common voltage terminal.